During semiconductor IC fabrication, 20 or more layers of material are successively deposited and patterned over a semiconductor substrate. Good function, performance and yield requires that the various layers be well aligned with each other. Additionally, with the advent of double patterning techniques, it is also important to be able to detect alignment errors between patterns formed by plural exposures on the same layer.
In order to detect and measure alignment errors, alignment marks are commonly placed in the scribe lines on the wafer. Several alignment marks are included, so that an average alignment error across the wafer can be determined. A variety of alignment mark shapes and sizes have been used. Generally, a first portion of the pattern is located on a first (lower) layer and a second portion of the pattern is located on a second (upper layer) above the first layer. The pattern portions are typically configured so that, when alignment is correct, the upper portion either directly overlies the lower portion, or a known spatial relationship is present between the upper and lower portion. Any deviation between the actual spatial relationship of the pattern portions and the expected relationship can be measured optically to determine the size of the alignment error.
As a general rule of thumb, alignment errors are maintained at less than 20% of the smallest dimension of any element of any of the patterns. As device sizes are reduced with each new technology node, the size of the allowable alignment error is correspondingly reduced. Improved overlay alignment error measurement methods and systems are desired.